A flash memory device is a non-volatile memory device, and thus, differs from other memory devices such as dynamic RAM (DRAM) or static RAM (SRAM) since it does not lose its memorized data in spite of being turned off. This feature makes the flash memory differ from.
In accordance with a cell array system, a flash memory device can be categorized into either an NOR type structure or a NAND structure. The NOR structure has cells aligned in parallel between a bit line and a ground while the NAND structure has cells aligned in series. The NOR flash memory enables a high-speed random access in performing a read operation, and thus, is widely used for mobile phone booting. On the other hand, the NAND flash memory device has a slow read speed and a fast write speed, and thus, is suitable for data storage and advantageous in downsizing.
In accordance with a structure of a unit cell, the flash memory can be categorized into a stacked gate type or a split gate type. According to a shape of a charge storage layer, the flash memory can be categorized into a floating gate device and an SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) device.
The floating gate device can include a floating gate formed of polysilicon surrounded by an insulator. Electric charges may be injected into the floating gate using channel hot carrier injection or discharged from the floating gate using Fowler-Nordheim tunneling. Thus, data can be stored or erased.
In 90 nm or below NOR flash memory device, a pre-metal dielectric (PMD) gap-fill process is very important. Since a spatial gap between gates may be very small, if spacers are provided to both sides of the gates, a PMD layer has a problem with voids. Therefore, it may be difficult to perform normal gap-filling. This void problem may enable the voids to be filled with a metallic substance such as tungsten and the like for filling a contact hole to electrically connect a first metal layer of a multilayered structure. Accordingly, the NOR flash memory device enables drains to be electrically connected using tungsten formed using CVD, thereby bringing about device failure.
As illustrated in example FIG. 1, a scanning electron microscope (SEM) image of a of 130 nm flash memory device in which a void-free normal gap-fill in PMD deposition is conducted.
As illustrated in example FIG. 2, if deposition of a 90 nm or below flash process is performed under the same processing conditions of the 130 nm flash process, undesirable voids may occur. This is due to an aspect ratio of the 90 nm flash process being rapidly increased to 1.93 despite that an aspect ratio of the 130 nm flash process is 1.05.
However, for a normal gap-fill without defects such as voids, the aspect ratio may be lowered by widening a space between gates or reducing thickness of spacers on both sides of the gates. If the spatial gap between the gates is increased, a breakdown voltage in a logic region requiring a high voltage is reduced, thereby causing problems such as reduced reliability in the cell region.
The thickness of the spacers may be reduced in order to reduce the aspect ratio between the gates. To further reduce the aspect ratio between the gates, the spacers can be etched. If the spacers are excessively etched, the thickness of the spacer in the logic region can be relatively reduced in order to reduce a channel length due to ion implantation. Thus, the breakdown voltage can be eventually lowered, resulting in problems to the device.
To reduce an aspect ratio, a spacer can be deposited having a thin thickness. If the thickness of the deposited spacer is thin, a breakdown voltage of the device may be lowered by subsequent ion implantation to reduce device reliability. Accordingly, after completion of ion implantation, a masking process may be additionally conducted in order to remove the spacer in the cell region, which increases fabricating costs.